ICS9FG1201H_11 Datasheet, PDF (11/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
SMBusTable: 1:1 PLL Frequency Selection
Byte 8 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
RESERVED
Bit 3
RESERVED
Bit 2
-
Frequency Select C
RW
Bit 1
-
Frequency Select B
RW
Bit 0
-
FS_A_410
RW
0
1
See 9FG1201H 1:1 PLL
Programming Table
PWD
0
0
0
0
0
x
1
Latch
SMBusTable: Reserved Register
Byte 9 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
SMBus Table: M/N Programming Enable
Byte 10 Pin #
Name
Bit 7
-
M/N_EN
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
Gear PLL and 1:1 PLL
M/N Programming RW
Enable
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
Disable
1
Enable
PWD
0
X
X
X
X
X
X
X
SMBus Table: Gear PLL Frequency Control Register
Byte 11 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
-
Gear PLL M Div5
RW
Bit 4
-
Gear PLL M Div4
RW
Bit 3
-
Gear PLL M Div3 M Divider Programming RW
Bit 2
-
Gear PLL M Div2
bits
RW
Bit 1
-
Gear PLL M Div1
RW
Bit 0
-
Gear PLL M Div0
RW
0
1
See 9FG1201H M/N
programming Table
PWD
X
X
X
X
X
X
X
X
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
11
1371F — 09/23/09