ICS9FG1201H_11 Datasheet, PDF (10/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
SMBusTable: Output Enable Readback Register
Byte 4 Pin #
Name
Control Function
Bit 7
46
Readback - FS_A_410
Bit 6
1
Readback - HIGH_BW# In
Bit 5
30
Readback - SMB_A2_PLLBYP# In
Bit 4
Reserved
Bit 3
Reserved
Bit 2
53
Readback - OE10_11# Input
Bit 1
44
Readback - OE9# Input
Bit 0
41
Readback - OE8# Input
Type
R
R
R
R
R
R
R
R
SMBusTable: Vendor & Revision ID Register
Byte 5 Pin #
Name
Control Function
Bit 7
-
RID3
Bit 6
-
Bit 5
-
RID2
RID1
REVISION ID
Bit 4
-
RID0
Bit 3
-
VID3
Bit 2
-
Bit 1
-
VID2
VID1
VENDOR ID
Bit 0
-
VID0
Type
R
R
R
R
R
R
R
R
SMBusTable: DEVICE ID
Byte 6 Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBusTable: Byte Count Register
Byte 7 Pin #
Name
Bit 7
-
BC7
Bit 6
-
BC6
Bit 5
-
BC5
Bit 4
-
BC4
Bit 3
-
BC3
Bit 2
-
BC2
Bit 1
-
BC1
Bit 0
-
BC0
Control Function Type
RW
RW
Writing to this register
configures how many
bytes will be read back.
RW
RW
RW
RW
RW
RW
0
1
Readback
Readback
Readback
Readback
Readback
Readback
Readback
Readback
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
PWD
X
X
X
X
0
0
0
1
PWD
1
1
0
0
0
0
0
1
PWD
0
0
0
0
1
0
0
1
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
10
1371F — 09/23/09