ICS9FG1201H_11 Datasheet, PDF (1/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &
FBD
ICS9FG1201H
Description
The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential
Buffer Specification. This buffer provides 12 output clocks for CPU
Host Bus, PCI-Express, or Fully Buffered DIMM applications. The
outputs are configured with two groups. Both groups (DIF 9:0) and
(DIF 11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B or CK410B+ main clock
generator, such as the ICS932S421, drives the ICS9FG1201. The
ICS9FG1201H can provide outputs up to 400MHz
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 50ps within a group
• DIF output-to-output skew < 100ps across all outputs
• 56-pin SSOP/TSSOP package
• RoHS compliant packaging
Features/Benefits
• Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
• Power up default is all outputs in 1:1 mode
• DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
• DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Functional Block Diagram
OE#
10
OE(9:0)#
SPREAD
COMPATIBLE
PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
2
LOGIC
DIF(11:10)
GEAR
SHIFT
LOGIC
STOP
10
LOGIC
DIF(9:0)
IREF
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1
1371F — 09/23/09