ICS9FG1201H_11 Datasheet, PDF (22/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
N
INDEX
AREA
12
D
c
L
E1 E
a
A2
A
A1
-C-
e
b
SEATING
PLANE
aaa C
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
--
0.10
--
.004
VARIATIONS
N
D mm.
MIN
MAX
56
13.90
14.10
Ref erence Doc.: JEDEC Publicat ion 95, M O-153
10-0039
D (inch)
MIN
MAX
.547
.555
Ordering Information
Part / Order Number
9FG1201HGLF
9FG1201HGLFT
9FG1201HFLF
9FG1201HFLFT
Shipping/Packaging
Tubes
Tape and Reel
Tubes
Tape and Reel
Package
56-pin TSSOP
56-pin TSSOP
56-pin SSOP
56-pin SSOP
Temperature
0 to +70°C
0 to +70°C
0 to +70°C
0 to +70°C
"LF" denotes Pb free packaging, RoHS compliant
"H" denotes revision designator (will not correlate with datasheet revision)
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
22
1371F — 09/23/09