English
Language : 

ICS9FG1201H_11 Datasheet, PDF (15/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Absolute Max
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
VDD_A
VDD_In
Ts
Tambient
Tcase
ESD prot
GND - 0.5
VDD + 0.5V V
1
GND - 0.5
VDD + 0.5V V
1
-65
150
°C
1
0
70
°C
1
115
°C
1
Human Body Model
2000
V
1
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS Notes
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Operating Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
Modulation Frequency
Tdrive_PD#
Tfall_Pd#
Trise_Pd#
SMBus Voltage
Low-level Output Voltage
Current sinking at
VOL = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
VIH
VIL
IIH
IIL1
VIH_FS
VIL_FS
IDD3.3OP
IDD3.3PD
Fi
Lpin
CIN
COUT
TSTAB
VMAX
VOL
IPULLUP
TRI2C
TFI2C
3.3 V +/-5%, Except CLK_IN
3.3 V +/-5%, Except CLK_IN
VIN = VDD
VIN = 0 V; Inputs with no pull-
up resistors
3.3 V +/-5%, Applies to
FS_A_410 pin
3.3 V +/-5%, Applies to
FS_A_410 pin
all outputs driven
all differential pairs tri-stated
VDD = 3.3 V
2
VSS - 0.3
-5
-5
0.7
VSS - 0.3
100
Logic Inputs
Output pin capacitance
From VDD Power-Up or de-
assertion of PD# to 1st clock
Triangular Modulation
30
DIF output enable after
PD# de-assertion
PD# fall time of
PD# rise time of
Maximum input voltage
@ IPULLUP
4
(Max VIL - 0.15) to
(Min VIH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
VDD + 0.3 V
1
0.8
V
1
5
uA
uA
VDD + 0.3 V
1
0.35
V
1
375
mA
1
24
mA
1
400 MHz 3
7
nH
1
5
pF
1
5
pF
1
1.8
ms
1
33
kHz
1
300
us
1
5
ns
1
5
ns
2
5.5
V
1
0.4
V
1
mA
1
1000
ns
1
300
ns
1
IDTTM/ICSTM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
15
1371F — 09/23/09