ICS9FG1201H_11 Datasheet, PDF (2/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Pin Configuration
HIGH_BW# 1
56 VDDA
CLK_IN 2
55 GNDA
CLK_IN# 3
54 IREF
SMB_A0 4
53 OE10_11#
OE0# 5
52 DIF_11
DIF_0 6
51 DIF_11#
DIF_0# 7
50 VDD
OE1# 8
49 GND
DIF_1 9
48 DIF_10
DIF_1# 10
47 DIF_10#
VDD 11
46 FS_A_410
GND 12
45 VTT_PWRGD#/PD
DIF_2 13
44 OE9#
DIF_2# 14
43 DIF_9
OE2# 15
42 DIF_9#
DIF_3 16
41 OE8#
DIF_3# 17
40 DIF_8
OE3# 18
39 DIF_8#
DIF_4 19
38 VDD
DIF_4# 20
37 GND
OE4# 21
36 DIF_7
VDD 22
35 DIF_7#
GND 23
34 OE7#
DIF_5 24
33 DIF_6
DIF_5# 25
32 DIF_6#
OE5# 26
31 OE6#
SMB_A1 27
30 SMB_A2_PLLBYP#
SMBDAT 28
29 SMBCLK
56-pin SSOP & TSSOP
Functionality Table
FS_A_410¹
CLK_IN (CPU FSB) DIF_(9:0) Output DIF_(11:10) Output
MHz
MHz
MHz
1
100.00
100.00
100.00
1
133.33
133.33
133.33
1
166.66
166.66
166.66
1
RESERVED
0
200.00
200.00
200.00
0
266.66
266.66
266.66
0
333.33
333.33
333.33
0
400.00
400.00
400.00
1. FS_A_410 is a low-threshold input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
2
1371F — 09/23/09