ICS9FG1201H_11 Datasheet, PDF (12/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
SMBus Table: Gear PLL Frequency Control Register
Byte 12 Pin #
Name
Control Function Type
Bit 7
-
Gear PLL N Div7
RW
Bit 6
-
Gear PLL N Div6
RW
Bit 5
-
Gear PLL N Div5
RW
Bit 4
-
Gear PLL N Div4 N Divider Programming RW
Bit 3
-
Gear PLL N Div3
bits
RW
Bit 2
-
Gear PLL N Div2
RW
Bit 1
-
Gear PLL N Div1
RW
Bit 0
-
Gear PLL N Div0
RW
0
1
See 9FG1201H M/N
programming Table
PWD
X
X
X
X
X
X
X
X
SMBusTable: Gear PLL Output Divider Register
Byte 13 Pin #
Name
Control Function Type
Bit 7
RESERVED
Bit 6
RESERVED
Bit 5
RESERVED
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GoutDiv 3
GoutDiv 2
GoutDiv 1
GoutDiv 1
RESERVED
RW
Gear Output Divider
RW
RW
RW
0
1
See Gear Output Divider
Table
PWD
0
0
0
0
X
X
X
X
SMBusTable: Reserved Register
Byte 14 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
SMBusTable: Reserved Register
Byte 15 Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function Type
0
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
1
PWD
0
0
0
0
0
0
0
0
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
12
1371F — 09/23/09