ICS9FG1201H_11 Datasheet, PDF (4/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Pin Description (continued)
Pin # Pin Name
29 SMBCLK
30 SMB_A2_PLLBYP#
31 OE6#
32 DIF_6#
33 DIF_6
34 OE7#
35 DIF_7#
36 DIF_7
37 GND
38 VDD
39 DIF_8#
40 DIF_8
41 OE8#
42 DIF_9#
43 DIF_9
44 OE9#
45 VTT_PWRGD#/PD
46 FS_A_410
47 DIF_10#
48 DIF_10
49 GND
50 VDD
51 DIF_11#
52 DIF_11
53 OE10_11#
54 IREF
55 GNDA
56 VDDA
Type
IN
IN
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
PWR
PWR
Pin Description
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
4
1371F — 09/23/09