ICS9FG1201H_11 Datasheet, PDF (18/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Electrical Characteristics - Phase Jitter
PARAMETER SYMBOL
CONDITIONS
MIN TYP. MAX
t_jphPCIe1
PCIe Gen 1 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54,
Td=10 ns, Ftrk=1.5 MHz )
40/38 86
t_jphPCIe2Lo
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Lo-band content
(10kHz to 1.5MHz)
1.3/1.2 3
Jitter, Phase
t_jphPCIe2Hi
PCIe Gen 2 REFCLK phase jitter
(including PLL BW 8 - 16 MHz,
ζ = 0.54, Td=12 ns)
Hi-band content
(1.5MHz to Nyquist)
3.0/2.4 3.1
t_{jphFBD1_3.2G}
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
2.8/2.3 3
t_{jphFBD1_4.8G}
FBD REFCLK phase jitter
(including PLL BW 11 - 33 MHz,
ζ = 0.54, Td=12 ns Ftrl=0.2MHz)
2.3/1.9 2.5
Notes on Phase Jitter:
1 _{See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production.}
2 _{Device driven by 932S421BGLF or equivalent}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1}-12
4 _{Hi-Bandwidth Number/Low Bandwidth Number with Spread On. Spread Off gives lower numbers.}
5 _{Byte 8 must be properly set to meet these parameters.}
UNITS
ps
ps rms
ps rms
ps
(RMS)
ps
(RMS)
NOTES
1,2,3,5
1,2,5
1,2,5
1,2,5
1,2,5
IDT^TM/ICS^TM Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
18
1371F — 09/23/09