STAC9766 Datasheet, PDF (88/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
13.1. Digital I/O
These signals connect the STAC9766/9767 to its AC'97 controller counterpart, an external crystal,
multi-CODEC selection and external audio amplifier.
Table 35. Digital Connection Signals
Pin Name
XTL_IN
XTL_OUT
SDATA_OUT
BIT_CLK
SDATA_IN
SYNC
RESET#
No Connect
No Connect
No Connect
GPIO0
GPIO1
CID0
CID1
EAPD
SPDIF
Pin #
2
3
5
6
8
10
11
31
33
34
43
44
45
46
47
48
Type
Description
I 24.576 MHz Crystal or External Clock Source
I/O 24.576 MHz Crystal
I Serial, time division multiplexed, AC'97 input stream
I/O 12.288 MHz serial data clock
O Serial, time division multiplexed, AC'97 output stream
I 48 KHz fixed rate sample sync
I AC'97 Master H/W Reset
I IDT Internal Test mode only.
I IDT Internal Test mode only
I/O IDT Internal Test mode only
I/O General Purpose I/O
I/O General Purpose I/O
I Multi-CODEC ID select – bit 0
I Multi-CODEC ID select – bit 1
I/O External Amplifier Power Down/GPIO
SPDIF digital output
I/O
Pin 48: To Enable SPDIF, use a 1KΩ - 1 0 KΩ external pulldown. To
Disable SPDIF, use a 1KΩ - 1 0 KΩ external pullup. Do NOT leave Pin 48
floating.
13.2. Filter/References
These signals are connected to resistors, capacitors, or specific voltages.
Table 36. Filtering and Voltage References
Signal Name
VREF
VREFOUT
AFILT1
AFILT2
CAP2
Pin Number Type
Description
27
O Analog ground (0.45*Vdd, at 5V; 0.41*Vdd at 3V)
28
O Reference Voltage out 5mA drive (intended for mic bias) (~Vdd/2)
29
O Anti-Aliasing Filter Cap - ADC left channel
30
O Anti-Aliasing Filter Cap - ADC right channel
32
O ADC Reference Cap
IDT™
88
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06