STAC9766 Datasheet, PDF (78/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
Bit(s) Reset Value Name
Description
15:8
0
RESERVED Reserved
0 = Anti Pop Enabled
1 = Anti Pop Disabled
The STAC9766/9767 includes an internal power supply anti-pop circuit that
prevents audible clicks and pops from being heard when the CODEC is powered
on and off. This function is accomplished by delaying the charge/discharge of the
7
0
INT_APOP ^{VREF capacitor (Pin 27). C VREF value of 1 µF will cause a turn-on delay of roughly}
3 seconds, which will allow the power supplies to stabilize before the CODEC
outputs are enabled. The delay will be extended to 30 seconds if a C_VREF value of
10 µF is used. The CODEC outputs are also kept stable for the same amount of
time at power-off to allow the system to be gracefully turned off. The INT_APOP bit
allows this delay circuit to be bypassed for rapid production testing. Any external
component anti-pop circuit is unaffected by the internal circuit.
6:0
0
RESERVED Reserved
8.4.11. EAPD Access Register (74h)
Default: 0800h
D15
EAPD
D7
D14
D13
D12
D11
D10
D9
D8
RESERVED
EAPD_OEN
RESERVED
D6
D5
D4
D3
D2
D1
D0
RESERVED
INTDIS GPIOACC GPIOSLT12
Bit(s) Reset Value Name
Description
15
0
EAPD
EAPD data Enable
EAPD data output on EAPD when bit D11 = 1
EAPD data input from pin when bit D11 = 0
14:12
0
RESERVED Bit not used, should read back 0
EAPD Pin Enable
11
1
EAPD_OEN 0 = EAPD configured as input pin
1 = EAPD configured as output pin
10:3
0
RESERVED Bit not used, should read back 0
Interrupt disable option.
Interrupts cleared by writing a 1 to I4 (Reg24h:D15)
2
0
INTDIS _{0 = will clear both SENSE and GPIO interrupts}
1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in
Reg54h.
GPIO ACCESS
1
0
GPIOACC 0 = ACLINK access from GPIO Pads
1 = ACLINK access from GPIO Register 54h
0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot12
data will be 0h.
1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs
0
0
GPIOSLT12 Reg54h will not be updated.
This can only be used if a modem CODEC is not present in the system and using
Slot12.
IDT™
78
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06