STAC9766 Datasheet, PDF (61/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
Note: If pin 48 is held high at powerup, the SPDIF is not available and bits D15:D1 can not be
written and will read back zero. Pin 48: To Enable SPDIF, use a 1KΩ - 1 0 KΩ external pulldown.
To Disable SPDIF, use a 1KΩ - 1 0 KΩ external pullup. Do NOT leave Pin 48 floating.
Bit(s) Reset Value
15
14-11
10
0
9:6
0
Name
VCFG
RESERVED
SPCV
RESERVED
Description
Determines the SPDIF transmitter behavior when data is not being
transmitted. When asserted, this bit forces the deassertion of the SPDIF
“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit
is defined in the SPDIF Control Register (Reg 3Ah).
If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),
bit<28> “Validity” flag reflects whether or not an internal CODEC
transmission error has occurred. Specifically an internal CODEC error
should result in the “Validity” flag being set to 1.
If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does
not receive a valid sample from the AC'97 controller, (Left or Right), the S/
PDIF transmitter should set the “Validity” flag to 0 and pad the “Audio
Sample Word” with 0 for sub-frame in question. If a valid sample (Left or
Right) was received and successfully transmitted, the “Validity” flag
should be 0 for that sub-frame.
Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.
These bits are set via driver .inf options.
Reserved
0 = Invalid SPDIF configuration
1 = Valid SPDIF configuration
Bit not used, should read back 0
SPDIF slot assignment
If CID[1:0] = 00 then SPSA[1:0] resets to 01
If CID[1:0] = 01 then SPSA[1:0] resets to 10
If CID[1:0] = 10 then SPSA[1:0] resets to 10
5:4
0
SPSA1:SPSA0 If CID[1:0] = 11 then SPSA[1:0] resets to 11
00 = Left slot 3, right slot 4
01 = Left slot 7, right slot 8
10 = Left slot 6, right slot 9
11 = Left slot 10, right slot 11
3
RESERVED Reserved
2
0
SPDIF
0 = Disables SPDIF (SPDIF_OUT is high Z) (note 1)
1 = Enable SPDIF
SPDIF is a control register for Reg 3Ah, this bit must be set low i.e. SPDIF
disabled in order to write to Reg 3Ah Bits D15,D13:D0.
1
0
RESERVED Bit not used, should read back 0
0 = VRA disabled, DAC and ADC set to 48 KHz (Registers 2Ch and 32h
0
0
VRA Enable loaded with the value BB80h)
1 = VRA ENABLED, Reg. 2Ch & 32h control sample rate
8.1.20.1. Variable Rate Sampling Enable
The Extended Audio Status Control register also contains one active bit to enable or disable the
Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1, the variable
IDT™
61
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06