STAC9766 Datasheet, PDF (60/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
ports the optional “AC’97 2.3 compliant AC-link slot to audio DAC mappings”.The default condition
assumes that 0, 0 are loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With
0s in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification rec-
ommendations. If the DSA1 and DSA0 bits do not contain 0s, the slot assignments are as per the
table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1
indicating that the CODEC supports the optional variable sample rate conversion as defined by the
AC’97 specification.
Table 20. Extended Audio ID Register Functions
Bit
Name
15:14 ID [1,0]
13:12
11:10
9:6
RESERVED
REV[1:0]
RSVD
Access
Read only
Read only
Read only
Read only
Reset Value
Variable
00
10
0
Function
00 = XTAL_OUT grounded (Note 1)
CID1#,CID0# = XTAL_OUT crystal or floating
Bits not used, should read back 00
Indicates CODEC is AC’97 Rev 2.3 compliant
Reserved
DAC slot assignment
5:4 DSA [1,0] Read/Write
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
00
If CID[1:0] = 11 then DSA[1:0] resets to 10
3
RSVD
Read only
2
SPDIF
Read only
1
RSVD
Read only
0
VRA
Read only
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
0
Reserved
1
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note 2)
0
Reserved
1
Variable sample rates supported (Always = 1)
1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin
45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in
primary mode only. Secondary mode can either be through BIT CLK driven or 24MHz clock
driver, with XTAL_OUT floating.
2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not avail-
able. Pin 48: To Enable SPDIF, use a 1KΩ - 1 0 KΩ external pulldown. To Disable SPDIF, use a
1 KΩ - 1 0 KΩ external pullup. Do NOT leave Pin 48 floating.
8.1.20. Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
D15
D14
VCFG
D7
D6
RESERVED
D13
D12
RESERVED
D5
D4
SPSA1
SPSA0
D11
D3
RSRVD
D10
SPCV
D2
SPDIF
D9
D8
RESERVED
D1
D0
RSRVD VRA enable
IDT™
60
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06