STAC9766 Datasheet, PDF (30/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
The VRM (Variable Rate Mic Audio) bit in the Extended Audio Status and Control Register controls
the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.
5.2.3. SLOTREQ Behavior and Power Management
SLOTREQ bits for fixed rate, powered down, and all unsupported slots should be driven with 0 for
maximum compatibility with the original AC '97 Component Specification. When a DAC channel is
powered down, it disappears completely from the serial frame: output tag and slot are ignored, and
the SLOTREQ bit is absent (forced to zero).
When the Controller wants to power-down a channel, all it needs to do is:
1. Disable source of DAC samples in Controller.
2. Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh.
When it wants to power up the channel, all it needs to do is:
1. Clear PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh.
2. Enable source of DAC samples in Controller.
5.2.4. Primary and Secondary CODEC Register Addressing
The 2-bit CODEC ID field in the LSBs of Output Slot 0 is an addition to the original AC-link protocol
that enables an AC‘97 Digital Controller to independently access Primary and Secondary CODEC
registers.
For Primary CODEC access, the AC‘97 Digital Controller:
1. Sets the AC-link Frame valid bit (Slot 0, bit 15).
2. Validates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13).
3. Sets a zero value (00) into the CODEC ID field (Slot 0, bits 1 and 0).
4. Transmits the desired Primary CODEC Command Address and Command Data in Slots 1 and
2.
For Secondary CODEC access, the AC‘97 Digital Controller:
1. Sets the AC-link Frame valid bit (Slot 0, bit 15).
2. Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0).
3. Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1
and 2.
Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13)
tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command
Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.
Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state
of the Secondary CODEC ID bits) if it is not valid. AC‘97 Digital Controllers should set the frame valid
bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the
Secondary CODEC ID bits are set.
IDT™
30
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06