STAC9766 Datasheet, PDF (63/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
8.1.21. PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs is controlled by the value in these read/write regis-
ters that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in
Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,
that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample
rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are
supported for record and playback.
Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h) will be loaded with BB80h
(48 KHz).
If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48 KHz.
Table 22. Hardware Supported Sample Rates
Sample Rate
8 KHz
11.025 KHz
16 KHz
22.05 KHz
32 KHz
44.1 KHz
48 KHz
SR15-SR0 Value
1F40h
2B11h
3E80h
5622h
7D00h
AC44h
BB80h
8.1.22. PCM DAC Rate (2Ch)
Default: BB80h (see table22: page63)
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
8.1.23. PCM LR ADC Rate (32h)
Default: BB80h (see table22: page63)
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
IDT™
63
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06