STAC9766 Datasheet, PDF (62/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
sample rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers
are allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.
The STAC9766/9767 supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot
in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-
fers and every audio frame will include an active slot request flag and data is transferred every
frame.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current
audio input frame for active output slots, which will require data in the next audio output frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. When VRA is set
to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
8.1.20.2. SPDIF
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the
SPDIF functionality within the STAC9766/9767. If the SPDIF is set to a 1, then the function is
enabled. When set to a 0, it is disabled.
8.1.20.3. SPCV (SPDIF Configuration Valid)
The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When
SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the sys-
tem configuration is valid.
8.1.20.4. SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
The STAC9766/9767 are AMAP compliant with the following table.
Table 21. AMAP Compliant
CODEC
ID
Function
SPSA = 00
SPSA = 01
SPSA = 10
SPSA = 11
slot assignment slot assignment slot assignment slot assignment
00 2-ch Primary w/SPDIF
3&4
7 & 8*
6&9
10 & 11
01 2-ch Dock CODEC w/SPDIF
3&4
7&8
6 & 9*
10 & 11
10 +2-ch Surr w/ SPDIF
3&4
7&8
6 & 9*
10 & 11
11 +2-ch Cntr/LFE w/ SPDIF
3&4
7&8
6&9
10 & 11*
Note: * is the default slot assignment
IDT™
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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06