STAC9766 Datasheet, PDF (13/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
2.2. AC Timing Characteristics
(T_{ambient =} 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3V ± 5%, AVss = DVss = 0 V; 7 5 pF external
load for BIT_CLK and 60pF external load for SDATA_IN)
2.2.1. Cold Reset
RESET#
Figure 2. Cold Reset Timing
Tres_low
Trst2clk
BIT_CLK
SDATA_IN
Ttri2actv
Ttri2actv
Parameter
RESET# active low pulse width
RESET# inactive to SDATA_IN or BIT_CLK active delay
RESET# inactive to BIT_CLK startup delay
BIT_CLK active to RESET# asserted (Not shown in diagram)
Symbol
Tres_low
Tri2actv
Trst2clk
Tclk2rst
Min
1.0
-
0.01628
0.416
Typ Max Units
-
-
µs
- 25 ns
- 400 µs
-
-
µs
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
2.2.2. Warm Reset
Figure 3. Warm Reset Timing
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
Symbol Min Typ Max
Tsync_high 1.0 1.3
-
Tsync2clk 162.8 -
-
Units
µs
ns
IDT™
13
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06