STAC9766 Datasheet, PDF (14/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
2.2.3. Clocks
Figure 4. Clocks Timing
Tclk_low
BIT_CLK
Tclk_high
Tclk_period
Tsync_low
SYNC
Tsync_high
Tsync_period
Parameter
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BLT_CLK high pulse width (Note 1)
BIT_CLK low pulse width (Note 1)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Note: 1. Worst case duty cycle restricted to 45/55.
Symbol
Min
Typ
Max
-
12.288
-
Tclk_period
-
81.4
-
-
750
-
Tclk_high
36
40.7
45
Tclk_low
36
40.7
45
-
48.0
-
Tsync_period
-
20.8
-
Tsync_high
-
1.3
-
Tsync_low
-
19.5
-
Units
MHz
ns
ps
ns
ns
KHz
µs
µs
µs
2.2.4. STAC9766/9767 Crystal Elimination Circuit and Clock Frequencies
The STAC9766/9767 supports several clock frequency inputs as described in the following table. In
general, when a 24.576 MHz xtal is not used, the XTALOUT pin should be tied to ground. This short
to ground configures the part into an alternate clock mode and enables an on board PLL.
CODEC Modes:
P = The STAC9766/9767 as a Primary CODEC
S = The STAC9766/9767 as a Secondary CODEC.
Table 1. Clock Mode Configuration
XTL_OUT
Pin Config
XTAL
XTAL or open
XTAL or open
XTAL or open
short to ground
short to ground
short to ground
short to ground
CID1
Pin Config
float
float
pulldown
pulldown
float
float
pulldown
pulldown
CID0
Pin Config
float
pulldown
float
pulldown
float
pulldown
float
pulldown
Clock Source Input
24.576MHz crystal
12.288 MHz BIT_CLK
12.288 MHz BIT_CLK
12.288 MHz BIT_CLK
14.31818 MHz source
27 MHz source
48 MHz source
24.576 MHz source
CODEC
Mode
P
S
S
S
P
P
P
P
CODEC
D
0
1
2
3
0
0
0
0
IDT™
14
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06