STAC9766 Datasheet, PDF (36/97 Pages) Integrated Device Technology – TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING

STAC9766/9767
TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
PC AUDIO
register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1
and 2 had been tagged “valid” by the AC‘97 CODEC during slot 0.
Table 9. Status Address Port Bit Assignments
Bit
19
18:12
11:2
1:0
Description
Reserved
Control Register Index
SLOTREQ
Reserved
Comments
Stuffed with 0
Echo of register index for which data is being returned
See Next Section
Stuffed with 0
The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions com-
municate the associated control register address, the next 10 bits support AC‘97’s variable sample
rate signaling protocol, and the trailing 2 bit positions are stuffed with 0 by AC‘97.
5.4.2.2. SLOTREQ signaling bits
AC-link input frame Slot 1, the Status Address Port, now delivers CODEC control register read
address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved
least significant bits have been defined as data request flags for output slots 3-12.
The AC-link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indi-
cates valid Status Address Port data (Control Register Index). The CODEC should only set
SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previ-
ous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the
Slot 1 tag bit.
SLOTREQ bits are always 0 in the following cases
• Fixed rate mode (VRA = 0)
• Inactive (powered down) ADC channel
SLOTREQ bits are only set to 1 by the CODEC in the following case
• Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48 KHz ADC
sample rate and CODEC does not need a sample
5.4.3. Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Table 10. Status Data Port Bit Assignments
Bit
Description
Comments
19:4
Control Register Read Data
Stuffed with 0 if tagged “invalid”
3:0
Reserved
Stuffed with 0
If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0 by AC‘97.
IDT™
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TWO-CHANNEL, 20-BIT, AC’97 2.3 CODECS WITH STEREO MICROPHONE AND MIC/JACK SENSING
STAC9766/9767
V 7.4 12/06