ICS1532 Datasheet, PDF (6/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
2.0.1 Pin Listing by Functional Grouping
Table 2-1. Pin Listing by Functional Group
Pin
Group
Pin
Name
Pin
Type
Pin Description
Pin #
Clock In
Clock In
Clock In
CLAMP
HSYNC
XIN
Clock Out ADCRCLK
Clock Out ADCSYNC
Clock Out CLK
Clock Out
Clock Out
Clock Out
Clock Out
Clock Out
Control In
Control In
MCLK
OSCOUT
PNLCLK
REF
XOUT
SCL
SBADR
Control In RESET
Control I/O SDA
Control
Out
PSEL1 - 3
Analog
Input
BLUE,
GREEN,
RED
Analog
Input
ABLUE_R
AGREEN_R
ARED_R
Data
Output
BA7 – BA0,
GA7 – GA0,
RA7 – RA0
Data
Output
BB7 – BB0,
GB7 – GB0,
RB7 – RB0
Clock In EXTFIL
Clock In PDEN/COAST
Input External CLAMP input - Optional
28
Input Horizontal Sync Input
6
Input Crystal Input - Connect 14.31818 MHz, 20pF, parallel resonance
106
crystal or and external 14.31818-MHz clock source
Output Analog-to-Digital Converter Reference Clock
54
• Half-rate pixel clock for latching digital output pixel data.
Output Analog-to-Digital Converter Sync
55
• Recovered HSYNC output. Latch with ADCRCLK.
Output Full Rate Pixel Clock to ADC Section
114
• Normally not used. See ADRCRCLK
Output Memory Clock - Independent user-programmable clock source #1 101
Output Oscillator Output - Native Oscillator or Divided Oscillator Output
113
Output Panel Clock - Independent user-programmable clock source #2
104
Output Reference - Various reference line clock sync signals.
112
Output Crystal Output - Connect to the crystal above or leave open
107
Input Serial Clock for I²C - 5-V tolerant input clock from an I²C bus
137
Input I²C Serial Bus Address
142
– Low, address is 49h for reads and 48h for writes
– High, address is 4Bh for reads and 4Ah for writes
Input RESET Input - Optional
142
– Low - Device held in RESET state
– High - Normal Operation -Pull high if unused
I/O Serial Data - 5-V tolerant pin data pin for an I²C bus
138
Output Programmable Outputs
See Register 37h.
8, 9, 10
Input
Analog Blue, Green and Red Inputs
15,
• Accepts analog data for the ADCs blue, green, and red converters 19,
22
Input Analog Blue, Green and Red Signal Returns
16,
• These pins provide a return path for the analog input data
20,
23
Output Blue ‘A’ 7–0, Green ‘A’ 7–0, and Red ‘A’ 7–0.
• Output first blue, green, and red digital pixel data, respectively.
• A7 = MSB
See
Figure 2-1
Output Blue ‘B’ 7–0, Green ‘B’ 7–0, and Red ‘B’ 7–0.
See
• Outputs second blue, green, and red digital pixel data, respectively. Figure 2-1
• A7 = MSB
Input External Filter-Optional external filter input between self and XFILRET 144
Input +5 Phase-Detector Enable - Can disable the charge pump with Reg 0:1-0 141
MDS 1532 G
6
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Revision 060804