ICS1532 Datasheet, PDF (15/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Table 4-2. New Register Set Outline (Continued)
Register Register Name Register
Index
Access
28h
MCLK-SS0 R/W. D-MK.
Bit # Bit Name
7-0 MCLK_SS0
29h
MCLK-SS1 R/W. D-MK. 7-4 Reserved
3-0 MCLK_SS1
Brief Description
Select MCLK spread-spectrum counter LSB’s bits 7-0
See Reg29 - Controls amount of frequency spread
Allowed Values = (288 *N / M) + 8
Reset
Value
0
Reserved
1010
Select MCLK spread-spectrum counter MSBs bits 11-8 0
See Reg28
2Ah
MCLK-SSOE R/W. D-MK. 7-6 MCLK_SS
Select MCLK spread-spectrum gain
0
– 00 = The gain is 1
– 01 = The gain is 2
– 10 = The gain is 4
– 11 = The gain is 8
5 Reserved
Reserved
0
4-2 MCLK_PFD
Select MCLK Phase/Frequency Detector gain
0
– 000 = Gain is 1
– 001 = Gain is 2
– 010 = Gain is 4
– 011 = Gain is 8
– 100 = Gain is 16, and so forth...
1-0 MCLK_OSD
Select value for MCLK Output Scaler Divider
0
– 00 = Divide by 1
– 01 = Divide by 2
– 10 = Divide by 4
– 11 = Divide by 8
2Bh
MCLK-OE
R/W
7-2 Reserved
1 MCLK_SSENB
0 MCLK_OE
Reserved
Enable MCLK spread-spectrum (1 = Enabled)
Enable MCLK output (1 = Enabled)
010000
0
0
2Ch
OUTPUT MUX R/W
7 High_Drive#
6 OE_OSC
5-4 OSC_Sel
3 Reserved
2 REFSEL
1-0 LCKSEL#
Disable high drive for ADC pixel data output pins
0
Enable OSCOUT output pin (1 = Enabled)
1
Select OSCOUT Output
0
– 00 = OSCOUT source is OSC.
– 01 = OSCOUT source is OSCDIVIDER (Reg7)
– 10 = OSCOUT source is OSC/2.
– 11 = Reserved
Reserved
0
Select REF status
0
Select active low output for STATUS (pin 111)
1
Low when selection below is properly locked, else high
– 00 = Main Pixel PLL
– 01 = MCLK: Memory Clock
– 10 = Reserved
– 11 = PNLCLK: Panel Clock
2Dh
PLL Reset
Write
7-4 MCLK_Reset
Writing 5xh resets MCLK PLL & loads Regs 26h~2Bh N/A
3-0 PNLCLK_Reset Writing xAh resets PNLCLK PLL & loads Regs 20~25h N/A
2Eh-2Fh Reserved
N/A
30h
ADC CTRL R/W
??????
7 ADC_OE
6 ADC_Inv
5 Force_ADC
Enable ADC output (1 = Enabled)
0
Invert ADCRCLK signal (1=Latch data on rising edge) 0
Force ADC Outputs to state of Reg30:3
1
MDS 1532 G
15
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Revision 060804