ICS1532 Datasheet, PDF (4/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
any appropriate, single ended source, typically a
crystal oscillator.
Either the conditioned HSYNC input or the loop output
(recovered HSYNC) is available at the FUNC pin, and
is aligned with the output clocks.
1.7 Dynamic Phase Adjust - DPA
The DPA is used for adjusting the phase relationship of
the main PLL’s re-generated clock to the incoming
analog data to assure properly sampled analog data.
The Dynamic Phase Adjust (DPA) allows a
programmable clock delay relative to the input HSYNC
signal. A delay of up to one clock period is
programmable: See Chapter 5, “DPA Operation” for
more details.
1.8 Clamps
The ICS1532 contains clamping circuitry to
compensate for non zero volt black levels on the
incoming video lines. Clamping causes the device to
charge internal level shifting capacitors to the
complementary voltage level of the analog input. This
guarantees that the input is in the proper voltage range
to be converted by the ADC and also has the effect of
making whatever the analog voltage level on the inputs
is during the Clamp interval, equal to approximately a
00 code.
Clamping may be initiated either internally, by the
ADCSYNC signal, or externally via the active high
CLAMP input pin. Typically, CLAMPing occurs just
after the HSYNC signal goes active. However, with the
externally input CLAMP signal, any area where the
incoming video is at the black level may be used.
1.9 Analog Amplifiers
The ICS1532 contains three independently controlled
analog amplifiers that prepare the incoming analog
inputs to be converted by the ADC. These amplifiers
have programmable gain and are to be adjusted by the
system so that the analog output code range is as wide
as practically possible.
1.10 Digital to Analog Converters
The Clamped output of the ICS1532’s Analog
Amplifiers is sent to the ADC’s to convert the analog
input’s into digital equivalents.
1.11 I²C Bus Serial Interface
The ICS1532 uses a 5 Volt tolerant, industry-standard
I²C-bus serial interface that runs at either low speed
(100 kHz) or high speed (400 kHz). The interface uses
4 banks of indexed registers: there are write-only,
read/write, and read-only registers.
Two ICS1532 devices can be addressed, according to
the state of the I2CADR pin. When this pin is low, the
read address is 49h, and the write address is 48h.
When the pin is high, the read address is 4Bh, and the
write address is 4Ah. See Chapter 10, “Programming”
1.12 Digital Inputs
All of the ICS1532’s digital inputs are 5 V-tolerant.
1.13 Digital Data Outputs
The ICS1532 uses slew controlled CMOS outputs and
are designed to be connected directly to the scaler or
data transmitter inputs with no series resistors.
1.14 Automatic Power-On Reset
Detection
The ICS1532 has automatic power-on reset detection
(POR) circuitry and it resets itself if the supply voltage
drops below ~1.8 VDC. No external connection to a
reset signal is required and it may be, but a active low
RESET# input is also provided and may be held low for
~10ms to reset the ICS1532.
1.15 Two Spread Spectrum Utility PLLs
Besides the Main, pixel clock PLL, the ICS1532 has
two other independent PLLs for use as needed.
Typically, these PLLs are used to drive memory and
panel data clocks. Both of these additional PLLs are
tailored for the required frequency ranges. Each
supports software-controlled spread-spectrum clock
dithering to reduce measured electro-magnetic
interference (EMI).
1.16 Programmable Outputs
For general-purpose outputs, the ICS1532 provides
programmable pins PSEL3, PSEL2, and PSEL1 (Reg
37:2-0).
MDS 1532 G
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Revision 060804