ICS1532 Datasheet, PDF (12/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
4.4 Complete Register Set
Table 4-2. New Register Set Outline
Register Register Name Register
Index
Access
00h
Input Control R/W
Bit # Bit Name
7-6 HSYNC_Sel
5 In_Sel
4 Fdbk Div Load
3 Fdbk_Pol
2 Ref_Pol
1 CP_Pol
0 CP_En
01h
Loop Control R/W. D-PLL. 7-6 Reserved
5-4 VCOS
3 Reserved
2-0 ICP
02h
Fdbk Div 0
R/W. D-PLL. 7-0 FDBK [7-0]
03h
Fdbk Div 1
R/W. D-PLL. 7-4 Reserved
3-0 FDBK [11-8]
04h
DPA Offset
R/W
7-6 Reserved
5-0 DPA_OS
Brief Description
Select HSYNC Input Threshold for Main PLL
– See Chapter 11-3, “Pin Specific I/O AC
Parameters”
Select Main PLL Phase Detector Input
– 0 = HSYNC source selected by Reg0:7-6
– 1 = Input is the OSC pin
Select load for Feedback Divider
– 0 = New values loaded on a pixel PLL
reset.-(Normal Operation)
– 1 = New values loaded on the HSYNC without a
PLL reset - Only usable for small changes
Select feedback polarity for Phase/Frequency Detector
– 0 = Main/Pixel PLL uses the rising edge
– 1 = Main/Pixel PLL uses the falling edge
Select polarity of external reference
– 0 = Rising HSYNC Edge Selected
– 1 = Falling HSYNC Edge Selected
Select polarity of COAST Input if Reg0:0=1
– 0 = Charge Pump enabled if COAST pin high
– 1 = Charge Pump enabled if COAST pin low
Charge Pump (CP) Enable
– 0 = CP enabled by Reg0:1 and COAST
– 1 = CP always Enabled - Normal Operation
Reset
Value
0
1
0
0
0
0
1
Reserved
0
Select VCO Scaler Value
0
VCO frequency = (Output frequency) * VCOS(d)
– 00 = 2:1
– 01 = 4:1
– 10 = 8:1
– 11 = 16:1
Reserved
0
ICP - Charge Pump Current
0
– 000 = ~2 μA
– 001 = ~4μA
– 010 = ~8μA (Typical with Internal Filter)
– 011 = ~16μA.
– 100 = ~32μA
– 101 = ~64μA
– 110 = ~120μA.
– 111 = ~190μA
Feedback Divider LSB’s bits 7-0 - See Reg3 for MSB’s N/A
– Controls the number of CLK outputs per HSYNC
– Actual # of CLK’s = 8 + (Reg3 + Reg2)d
Reserved
–
Feedback Divider MSB’s bits 11-8 - See Reg2
N/A
Reserved
0
Dynamic Phase Adjust (DPA) Offset
0
– See Chapter 5, “DPA Operation”
The value programmed here must be less than the
DPA Resolution controlled by Reg5:1-0
MDS 1532 G
12
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Revision 060804