ICS1532 Datasheet, PDF (13/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Table 4-2. New Register Set Outline (Continued)
Register Register Name Register Bit #
Index
Access
Bit Name
Brief Description
Reset
Value
05h
DPA Control R/W. D-DPA. 7-2 Reserved
1-0 DPA_Res
Reserved
–
DPA resolution (Number of available Delay Elements) N/A
See Chapter 5, “DPA Operation”
– 00 = 16 elements - supports 55 to 110 MHz
– 01 = 32 elements - supports 27 to 110 MHz
– 10 = Reserved
– 11 = 64 elements - supports 14 to 64 MHz
06h
Output Enables R/W
7 Reserved
Reserved
0
6 OE_TCLK
Enable CLK output to ADC and CLK pin
0
1 = MUST be Enabled for Normal Operation
5 OE_ADCRCLK Enable ADCRCLK clock output
0
4 OE_ADCSYNC Enable output for ADCSYNC
0
3 FUNC_Sel
Select signal source for ADC_FUNC signal
0
0 = Output of the Feedback Divider - Normal Operation
1 = ADC_FUNC output is REF
2 FUNC_Delay
Additional one CLK delay for ADC_FUNC signal
0
1 Reserved
Reserved
0
0 Reserved
Reserved
0
07h
OSC Divider R/W
7-0 OSC_Div
Oscillator divider value
0
– 00000000 = Reserved.
– 00000001 = (OSC / 2)
– 00000010 = (OSC / 2) / 2
– 00000011 = (OSC / 2) / 3, and so forth.
1
OSC Period
2
3
08h
Internal Filter R/W
7 Shunt_Sel
Select additional Cp capacitor
1
Values?
6-4 Res_Sel
Select additional Rs resistance
7
Values?
3-1 Cap_Sel
Select additional Cs capacitance
7
0 Fil_Sel
Selects Loop Filter Select
1
1 = Internal (Typical)
0=External
09h
Reserved
N/A
0Ah
Pixel PLL/
Write
DPA Resets
7-4 Pixel PLL Reset Writing 5xh resets pixel PLL and loads working Regs N/A
1h through 3h
3-0 DPA Reset
Writing xAh resets DPA and loads working Reg 5h
N/A
0Bh-0Fh Reserved
N/A
10h
Chip Ver
Read
7-0 Chip Ver
Read chip version 32 decimal (20h) as in 1532
20
11h
Chip Rev
Read. IN-A. 7-4 Chip Major Rev Value increments with major chip revision.
01
MDS 1532 G
13
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Revision 060804