ICS1532 Datasheet, PDF (3/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Chapter 1 Summary
The ICS1532 is the ideal device for capturing analog
RGB from a personal computer or other sources into
the digital domain for display on a digital device such
as an LCD panel. Contained inside the ICS1532 device
are the following blocks to accomplish this:
•Main PLL - Re-generates required clock for sampling
analog input data
•DPA - Adjusts the phase of the sampling clock.
•Clamps - Controls the ADC’s zero code value.
•Amplifiers - Controls the ADC’s full scale code value.
•ADC - Three ADCs converts the analog input into
digital.
•I2C - Standard I²C bus used for controlling the device
•POR - Power on reset for the I2C interface
•Two Spread Spectrum Utility PLLs - For generating
any other clocks needed by the system.
1.1 Main Phase-Locked Loop (PLL)
Main PLL- The main PLL is used for re-generating the
clocks needed to properly sample the incoming analog
signals.
Figure 1-1 Simplified PLL Diagram
The heart of the ICS1532 is a voltage controlled
oscillator (VCO). The VCO’s speed is controlled by the
voltage on the loop filter. This voltage will be described
later in this section.
1.2 VCO Divider (VCOD)
The VCO’s clock output is first passed through the
VCO Divider (VCOD). The VCOD allows the VCO to
operate at higher speeds than the required output
clock.
NOTE: Under normal, locked operation the VCOS has
no effect on the speed of the output clocks, just the
VCO frequency.
1.3 Dynamic Phase Adjust (DPA)
The output of the VCOS is then sent through the
Dynamic Phase Adjust (DPA) for phase adjustment
and also the 12 bit internal Feedback Divider. The
feedback divider controls how many clocks are seen
during every cycle of the input reference.
1.4 Feedback Divider (FBD)
The feedback divider output is a 4 CLK wide signal
called ADCSYNC. The ADCSYNC signal is aligned
with the output clocks and is intended to be used by
the system as a replacement for the HSYNC input,
which is of indeterminate quality and is not aligned with
the output clocks.
1.5 Phase Frequency Detector (PFD)
The Phase Frequency Detector (PFD) then compares
ADCSYNC to the selected input HSYNC and controls
the filter voltage by enabling and disabling the charge
pump. The charge pump has programmable current
drive and will source and sink current as appropriate to
keep the input HSYNC and the ADCSYNC output
aligned.
The PFD’s HSYNC input is conditioned by a
high-performance Schmitt trigger. This preconditioned
HSYNC signal, called REF, is provided as a clean
reference signal with a short transition time can be
output on pin 112.
1.6 OSC Input
The high-frequency OSC input pin, has a 7-bit user
programmable divider can also be selected as the loop
input. This selection allows the loop to operate from
MDS 1532 G
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Revision 060804