ICS1532 Datasheet, PDF (22/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
10.2 Programming Flow for Modifying PLL and DPA Settings
Figure 10-2. ICS1532 Flow for Capture/Input Clock PLL
Start
Scaler
Determ ines
mode
Changing PLL
Param eters?
YES
Set Input, PFD Gain, Post
Adjust
PFD Gain
Scaler and Feedback Divider
Regs 0~3
and/or
Post Scaler
NO
PLL S/W
Reset
RegA=50h
NO
PLL Locked?
YES
Set
DPA Resolution, Reg5
and DPA Offset, Reg4
Adjust
DPA offset
Reg4
DPA S/W
Reset
RegA=0Ah
MDS 1532 G
NO
Correct Phase
Relationship?
YES
Done
22
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Revision 060804