ICS1532 Datasheet, PDF (29/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Chapter 12 Timing Diagrams
12.1 AC Timing Diagrams
12.1.1 Phase-Locked-Loop Timing for Digital Setup and Hold
The input HSYNC signal is used to generate the REF output signal. In the Phase/Frequency Detector, the
REF signal is compared with ADCSYNC (which provides the recovered HSYNC signal). Table 12-1 gives
the timing for these signals, and Figure 12-1 shows timing characteristics.
Table 12-1. Phase-Locked-Loop Timing
Time
Period
Timing Description
t1 Input HSYNC Rise Time to
REF Rise Time
Tp ADCRCLK Period
Min
TBD
Tp =
Typ
7
Input HSYNC Frequency
(Reg 03 and 02) + 8
Max Units
TBD ns
ns
Td ADCRCLK Duty Cycle
t2 ADCSYNC Active Time
45-55
50-50
4 x Tp
55-45 %
ns
Figure 12-1. Timing for Phase-Locked Loop
HSYNC
t1
REF
Tp
Td
CLK
t2
ADCSYNC
MDS 1532 G
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Revision 060804