ICS1532 Datasheet, PDF (14/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Table 4-2. New Register Set Outline (Continued)
Register Register Name
Index
Register
Access
Bit # Bit Name
3-0 Chip Minor Rev
Brief Description
Value increments with minor chip revision.
Reset
Value
00
12h
Rd_Reg
Read
7-4 Reserved
3 PLL_Lock
2 MCLK_Lock
1 PCLK_Lock
0 Reserved
Reserved
N/A
Pixel PLL lock status - 1 = Locked, 0 = Unlocked
N/A
Memory MCLK lock status - 1 = Locked, 0 = Unlocked N/A
Panel PLL lock status - 1 = Locked, 0 = Unlocked
N/A
Reserved
N/A
13h-1Fh Reserved
N/A
20h
PNLCLK-M R/W. D-PK. 7-0 PNLCLK_M
Select value for PNLCLK M Reference Divider
0
21h
PNLCLK-N
R/W. D-PK. 7-0 PNLCLK_N
Select value for PNLCLK N Feedback Divider
0
F_PNLCLK = (OSC x (N + 8) / (M+2)
22h
PNLCLK-SS0 R/W. D-PK. 7-0 PNLCLK_SS0 Value for PNLCLK spread-spectrum counter LSB’s bits 0
7-0 - Controls amount of frequency spread
Allowed Values = (288 *N / M) + 8
23h
PNLCLK-SS1 R/W. D-PK. 7-4 Reserved
Reserved
0
3-0 PNLCLK_SS1 Value for PNLCLK spread-spectrum counter MSBs bits 0
11-8 See Reg22
24h
PNLCLK-SSOE R/W. D-PK. 7-6 PNLCLK_SS
Select PNLCLK spread-spectrum gain
0
– 0 = The gain is 1
– 1 = The gain is 2
– 2 = The gain is 4
– 3 = The gain is 8
5 Reserved
Reserved
0
4-2 PNLCLK_PFD PNLCLK Phase/Frequency Detector gain
0
– 000 = Gain is 1
– 001 = Gain is 2
– 010= Gain is 4
– 011 = Gain is 8, and so forth...
– 111 = Gain is 128
1-0 PNLCLK_OSD PNLCLK Output Scaler Divider
0
– 00 = Divide by 1
– 01 = Divide by 2
– 10= Divide by 4
– 11 = Divide by 8
25h
PNLCLK-OE R/W
7-3 Reserved
Reserved
2 CLK_SEL
Select input for PNLCLK PLL
– 0 = PNLCLK PLL input is from the crystal input
– 1 = Input is from ADC_CLK, divided by 16
1 PNLCLK_SSENB Enable PNLCLK spread-spectrum
0 PNLCLK_OE
Enable PNLCLK output
11100
0
0
0
26h
MCLK-M
R/W. D-MK. 7-0 MCLK_M
Value for MCLK M Feedback Divider
0
27h
MCLK-N
R/W. D-MK. 7-0 MCLK_N
Value for MCLK N (Numerator) Feedback Divider
0
F_MCLK = (OSC x (N + 8)) / (M+2)
MDS 1532 G
14
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Revision 060804