ICS1532 Datasheet, PDF (18/36 Pages) Integrated Device Technology – 110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR

ICS1532
110 MHZ TRIPLE 8-BIT ADC WITH CLOCK GENERATOR
Chapter 5 DPA Operation
Figure 5-1. DPA Offset (As Determined by Regs 04 and 05)
HSYNC
Fixed delay ≈ 2.5 ns
CLK Offset when
DPA_OS [5-0] = 0
CLK Offset when
DPA_OS [5-0] = 1
CLK Offset when
DPA_OS [5-0] = 2
.
.
.
.
.
.
CLK Offset when
DPA_OS [5-0] = Max
One clock period
t_High
t_Low
1 unit of DPA delay
t_High
2 units of DPA delay
t_High
Maximum units of DPA delay
One unit of
DPA Delay
t_High
Table 5-1. DPA Control
Reg 05:1-0
Bit 1 Bit 0
0
0
0
1
1
0
1
1
1. Number of Delay
Element Units
(Decimal)
16
32
Reserved
64
2. Reg 04:5-0
Max. Value
(Hex)
0F
1F
Reserved
3F
27
14
3. Pixel Clock Range
(MHz)
55
110
110
64
MDS 1532 G
18
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Revision 060804