DT72T1845 Datasheet, PDF (6/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PARTIAL RESET (PRS) MASTER RESET (MRS)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
WRITE CHIP SELECT (WCS)
LOAD (LD)
(x18, x9) DATA IN (D0 - Dn)
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
READ CHIP SELECT (RCS)
(x18, x9) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5909 drw03
INPUT WIDTH (IW) OUTPUT WIDTH (OW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
L
L
x18
L
H
x18
H
L
x9
H
H
x9
Read Port Width
x18
x9
x18
x9
6