DT72T1845 Datasheet, PDF (20/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER
8 76543
D/Q0
21
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
16 15 14 13 12 11 10 9
1st Parallel Offset Write/Read Cycle
D/Q8
EMPTY OFFSET REGISTER
8 7 65 4 3
D/Q0
21
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
16 15 14 13 12 11 10 9
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
20 19 18 17
3rd Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER
8 7 6 54 3
D/Q0
21
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
16 15 14 13 12 11 10 9
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895⁽¹⁾⎯ x9 Bus Width
4th Parallel Offset Write/Read Cycle
D/Q8
FULL OFFSET REGISTER
8 7 65 4 3
D/Q0
21
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
16 15 14 13 12 11 10 9
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
20 19 18 17
IDT72T1895/72T18105/72T18115/72T18125⁽¹⁾⎯ x9 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
EMPTY OFFSET REGISTER
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
Non-Interspersed
Parity
Interspersed
Parity
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET REGISTER
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895⎯ x18 Bus Width
x9 to x9 Mode
# of Bits Used:
12 bits for the IDT72T1845
13 bits for the IDT72T1855
14 bits for the IDT72T1865
15 bits for the IDT72T1875
16 bits for the IDT72T1885
17 bits for the IDT72T1895
18 bits for the IDT72T18105
19 bits for the IDT72T18115
20 bits for the IDT72T18125
Note: All unused bits of the
LSB & MSB are don’t care
All Other Modes
# of Bits Used:
11 bits for the IDT72T1845
12 bits for the IDT72T1855
13 bits for the IDT72T1865
14 bits for the IDT72T1875
15 bits for the IDT72T1885
16 bits for the IDT72T1895
17 bits for the IDT72T18105
18 bits for the IDT72T18115
19 bits for the IDT72T18125
Note: All unused bits of the
LSB & MSB are don’t care
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (LSB) REGISTER
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (MSB) REGISTER
19 18 17
19 18 17
Non-Interspersed
Parity
Interspersed
Parity
3rd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
FULL OFFSET (LSB) REGISTER
16 15 14 13 12 11 10 9 8 7 6 5 4 3
16 15 14 13 12 11 10 9 8 7 6 5 4 3
D/Q8
D/Q0
21
21
4th Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
D/Q0
FULL OFFSET (MSB) REGISTER
4666 drw 06
19 18 17
19 18 17
IDT72T18105/72T18115/72T18125⎯ x18 Bus Width
5909 drw07
NOTES:
1. When programming the IDT72T1895 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72T1895 with an output
bus width of x9 and input bus width of x18, 4 read cycles will be required. A total of 6 program/read cycles will be required if both the input and output bus widths are set to x9.
2. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
20