DT72T1845 Datasheet, PDF (29/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAG TIMING SPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
TRST
t6
t5
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
tDO
5909 drw10
Figure 6. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
Parameter Symbol Test Conditions Min. Max. Units
Data Output
tDO⁽¹⁾
- 20 ns
Data Output Hold tDOH⁽¹⁾
0
- ns
Data Input
tDS
tDH
trise=3ns
tfall=3ns
10
- ns
10
-
NOTE:
1. 50pf loading on external output signals.
JTAG
AC ELECTRICAL CHARACTERISTICS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
Parameter
Symbol Test
Conditions
Min. Max. Units
JTAG Clock Input Period tTCK
-
100 - ns
JTAG Clock HIGH
tTCKHIGH
-
40 - ns
JTAG Clock Low
tTCKLOW
-
40 - ns
JTAG Clock Rise Time tTCKRISE
-
- 5⁽¹⁾ ns
JTAG Clock Fall Time tTCKFALL
-
- 5⁽¹⁾ ns
JTAG Reset
tRST
-
50 - ns
JTAG Reset Recovery tRSR
-
50 - ns
NOTE:
1. Guaranteed by design.
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