DT72T1845 Datasheet, PDF (36/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
D0 - Dn
FF
t ⁽¹⁾
SKEW1
NO WRITE
1
tCLKH
2
tDS
tCLK
tCLKL
tDH
DX
tWFF
tWFF
t ⁽¹⁾
SKEW1
NO WRITE
1
2
tDS
tDH
tWFF
DX+1
tWFF
WEN
RCLK
REN
RCS
tENS
tENS
tENH
tENS
tENH
Q0 - Qn
tA
tRCSLZ
tA
DATA READ
NEXT DATA READ
5909 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
RCLK
tENS
REN
EF
Q0 - Qn
OE
WCLK
WEN
tENH
tREF
1
NO OPERATION
tA
tOLZ
tOE
tSKEW1⁽¹⁾
LAST WORD
tENS
tENH
tOHZ
tCLKH
2
NO OPERATION
tREF
tCLK
tCLKL
tENS
tENH
tA
LAST WORD
tOLZ
tENS
tENH
tENS
D0
tENH
tREF
tA
D1
WCS
D0 - Dn
tWCSS
tDS
tDH
D0
tWCSH
tDS
tDH
D1
5909 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
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