DT72T1845 Datasheet, PDF (19/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
LD WEN REN SEN ^WCLK
001 1
RCLK
IDT72T1845,
IDT72T1865,
IDT72T1885,
IDT72T18105,
IDT72T18125
IDT72T1855
IDT72T1875
IDT72T1895
IDT72T18115
X
x18 input
Parallel write to registers:
x18 input
x9 input
x9 input
(72T18105/115/125)
(72T1895/105/115/125)
Empty Offset Empty Offset (LSB) Empty Offset (LSB) Empty Offset (LSB)
Full Offset Empty Offset (MSB) Empty Offset (MSB) Empty Offset
Full Offset (LSB) Full Offset (LSB) Empty Offset (MSB)
Full Offset (MSB) Full Offset (MSB) Full Offset (LSB)
Full Offset
Full Offset (MSB)
010 1
X
011 0
X1 1 1
X
Parallel read from registers:
x18 input
x18 input
x9 input
x9 input
(72T18105/115/125)
(72T1895/105/115/125)
Empty Offset Empty Offset (LSB) Empty Offset (LSB) Empty Offset (LSB)
Full Offset Empty Offset (MSB) Empty Offset (MSB) Empty Offset
Full Offset (LSB) Full Offset (LSB) Empty Offset (MSB)
Full Offset (MSB) Full Offset (MSB) Full Offset (LSB)
Full Offset
Full Offset (MSB)
x9 to x9 Mode
All Other Modes
Serial shift into registers:
X
24 bits for the IDT72T1845
26 bits for the IDT72T1855
28 bits for the IDT72T1865
30 bits for the IDT72T1875
32 bits for the IDT72T1885
34 bits for the IDT72T1895
36 bits for the IDT72T18105
38 bits for the IDT72T18115
40 bits for the IDT72T18125
Serial shift into registers:
22 bits for the IDT72T1845
24 bits for the IDT72T1855
26 bits for the IDT72T1865
28 bits for the IDT72T1875
30 bits for the IDT72T1885
32 bits for the IDT72T1895
34 bits for the IDT72T18105
36 bits for the IDT72T18115
38 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
10XX
X
Write Memory
1X0 X
X
Read Memory
111 X
X
X
No Operation
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
5909 drw06
Figure 3. Programmable Flag Offset Programming Sequence
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