DT72T1845 Datasheet, PDF (25/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state. During Master or a Partial Reset the OE is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only
input that provides High-Impedance control of the Qn outputs. If OE is LOW the
Qn data outputs will be Low-Impedance regardless of RCS until the first rising
edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs
will go to High-Impedance.
The RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the EF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user must take care when
a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when
an empty FIFO is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take RCS active LOW to access this first word, place the output bus in LOW-Z.
REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.
A rising edge of RCLK with RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when RCS is HIGH. Refer to Figure 17, RCS and REN Read Operation
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform
a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT
Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then RCS
must be held active, (tied LOW). OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
The control inputs, data inputs and flag outputs associated with the write port
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
The control inputs, data inputs and flag outputs associated with the read port
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
SYSTEM HSTL SELECT (SHSTL)
All inputs not associated with the write and read port can be setup to be either
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the LD pin is used to activate the programming process
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
BUS-MATCHING (IW, OW)
The pins IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for Bus-
Matching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN (BE)
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when data is written into the FIFO in word format (x18) and read out
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected, then the most significant byte of the word written into the FIFO will be
read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mable flag timing mode. If asynchronous PAF/PAE configuration is selected
(PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of
WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D0-Dn)
when programming the flag offsets. If Interspersed Parity mode is selected, then
the FIFO will assume that the parity bit is located in bit position D8 and D17 during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
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