DT72T1845 Datasheet, PDF (21/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 24 bits for the
IDT72T1845, 26 bits for the IDT72T1855, 28 bits for the IDT72T1865, 30 bits
for the IDT72T1875, 32 bits for the IDT72T1885, 34 bits for the IDT72T1895,
36 bits for the IDT72T18105, 38 bits for the IDT72T18115 and 40 bits for the
IDT72T18125. For any other mode of operation (that includes x18 bus width
on either the Input or Output), minus 2 bits from the values above. So, a total
of 22 bits for the IDT72T1845, 24 bits for the IDT72T1855, 26 bits for the
IDT72T1865, 28 bits for the IDT72T1875, 30 bits for the IDT72T1885, 32 bits
for the IDT72T1895, 34 bits for the IDT72T18105, 36 bits for the IDT72T18115
and 38 bits for the IDT72T18125. See Figure 20, Serial Loading of Program-
mable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF will be valid after three more rising WCLK edges plus tPAF, PAE will be valid
after the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. If the FIFO is configured for an input
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 4 for the IDT72T1845/
72T1855/72T1865/72T1875/72T1885 or 6 for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
gramming Sequence, for a detailed diagram of the data input lines D0-Dn used
during parallel programming. If the FIFO is configured for an input to output bus
width of x9 to x18, x18 to x9 or x18 to x18, then the following number of write
operations are required. For an input bus width of x18 a total of 2 write operations
will be required to program the offset registers for the IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895 or 4 for the IDT72T18105/72T18115/
72T18125. For an input bus width of x9 a total of 4 write operations will be
required to program the offset registers for the IDT72T1845/72T1855/72T1865/
72T1875/72T1885. A total of 6 will be required for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
gramming Sequence, for a detailed diagram.
For example, programming PAE and PAF on the IDT72T1895 configured
for x18 bus width proceeds as follows: when LD and WEN are set LOW, data
on the inputs Dn are written into the LSB of the Empty Offset Register on the first
LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition
of WCLK, data are written into the MSB of the Empty Offset Register. On the third
LOW-to-HIGH transition of WCLK, data are written into the LSB of the Full Offset
Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into
the MSB of the Full Offset Register. The fifth LOW-to-HIGH transition of WCLK,
data are written, once again to the Empty Offset Register. Note that for x9 bus
width, one extra Write cycle is required for both the Empty Offset Register and
Full Offset Register. See Figure 21, Parallel Loading of Programmable Flag
Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when LD is set LOW and REN is set LOW. It is important to note that
consecutive reads of the offset registers is not permitted. The read operation must
be disabled for a minimum of one RCLK cycle in between offset register
accesses. If the FIFO is configured for an input bus width and output bus width
both set to x9, then the total number of read operations required to read the offset
registers is 4 for the IDT72T1845/72T1855/72T1865/72T1875/72T1885 or 6
for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure 3,
Programmable Flag Offset Programming Sequence, for a detailed diagram
of the data input lines D0-Dn used during parallel programming. If the FIFO is
configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18,
then the following number of read operations are required: for an output bus
width of x18 a total of 2 read operations will be required to read the offset registers
for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 or 4 for
the IDT72T18105/72T18115/72T18125. For an output bus width of x9 a total
of 4 read operations will be required to read the offset registers for the
IDT72T1845/72T1855/72T1865/72T1875/72T1885. A total of 6 will be re-
quired for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure
3, Programmable Flag Offset Programming Sequence, for a detailed diagram.
See Figure 22, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
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