DT72T1845 Datasheet, PDF (17/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
(4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865,
(16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885,
(65,536-m) writes for the IDT72T1895, (131,073-m) writes for the IDT72T18105,
(262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m)
= (4,097-m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855,
(16,385-m) writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875,
(65,537-m) writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895,
(262,145-m) writes for the IDT72T18105, (524,289-m) writes for the
IDT72T18115 and (1,048,577-m) writes for the IDT72T18125. The offset m
is the full offset value. The default setting for these values are stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049
writes for the IDT72T1845, 4,097 writes for the IDT72T1855, 8,193 writes for
the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the
IDT72T18105, 262,145 writes for the IDT72T18115 and 524,289 writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,097
writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes
for the IDT72T1865, 32,769 writes for the IDT72T1875, 65,537 writes for the
IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the
IDT72T18105, 524,289 writes for the IDT72T18115 and 1,048,577 writes for
the IDT72T18125, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
IDT72T1845
Offsets n,m
All Other
x9 to x9
*LD
FSEL1 FSEL0
Modes
Mode
L
H
L
511
511
L
L
H
255
255
L
L
L
127
127
L
H
H
63
63
H
L
L
31
1,023
H
H
L
15
31
H
L
H
7
15
H
H
H
3
7
IDT72T1855, 72T1865, 72T1875, 72T1885,
72T1895, 72T18105, 72T18115, 72T18125
*LD
FSEL1 FSEL0
H
L
L
Offsets n,m
1,023
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
H
L
31
H
L
H
15
H
H
H
7
*LD
FSEL1 FSEL0
Program Mode
H
X
X
Serial⁽³⁾
L
X
X
Parallel⁽⁴⁾
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is resettoHIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25
for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.
17