DT72T1845 Datasheet, PDF (30/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/72T18125 in-
corporates the necessary tap controller and modified pad cells to implement the
JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
• Test Access Port (TAP)
• TAP controller
• Instruction Register (IR)
• Data Register Port (DR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture.
TDO
TDI
T
A
TMS ^P
TCLK
TRST
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
Mux
clkDR, ShiftDR
UpdateDR
TAP
Cont-
roller
clklR, ShiftlR
UpdatelR
Instruction Decode
Instruction Register
Control Signals
5909 drw11
Figure 7. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
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