DT72T1845 Datasheet, PDF (1/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

2.5 VOLT HIGH-SPEED TeraSync™ FIFO
18-BIT/9-BIT CONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
*IDT72T1845, *IDT72T1855
*IDT72T1865, *IDT72T1875
*IDT72T1885, *IDT72T1895
IDT72T18105, IDT72T18115
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
IDT72T18125
*SPECIFIED PRODUCTS ARE EOL - LAST TIME BUY EXPIRES MAY 26, 2018
FEATURES:
• Choose among the following memory organizations:
IDT72T1845 ⎯ 2,048 x 18/4,096 x 9
IDT72T1855 ⎯ 4,096 x 18/8,192 x 9
IDT72T1865 ⎯ 8,192 x 18/16,384 x 9
IDT72T1875 ⎯ 16,384 x 18/32,768 x 9
IDT72T1885 ⎯ 32,768 x 18/65,536 x 9
IDT72T1895 ⎯ 65,536 x 18/131,072 x 9
IDT72T18105 ⎯ 131,072 x 18/262,144 x 9
IDT72T18115 ⎯ 262,144 x 18/524,288 x 9
IDT72T18125 ⎯ 524,288 x 18/1,048,576 x 9
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information
• For IDT72T1845/55/65/75/85/95 functional replacement device use
IDT72T18125
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK/WR
WCS
D0 -Dn (x18 or x9)
LD SEN SCLK
INPUT REGISTER
OFFSET REGISTER
ASYW
BE
IP
WRITE CONTROL
LOGIC
WRITE POINTER
CONTROL
LOGIC
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
FLAG
LOGIC
READ POINTER
IW
OW
MRS
PRS
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
OE
Q0 -Qn (x18 or x9)
EREN
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
RT
MARK
ASYR
RCLK/RD
REN
RCS
5909 drw01
MAY 2017
DSC-5909/20