DT72T1845 Datasheet, PDF (16/56 Pages) Integrated Device Technology – 2.5 VOLT HIGH-SPEED TeraSync™ FIFO

IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 support two different timing modes of opera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 1,025th word for the IDT72T1845, 2,049th word for
IDT72T1855, 4,097th word for the IDT72T1865, 8,193rd word for the
IDT72T1875, 16,385th word for the IDT72T1885, 32,769th word for the
IDT72T1895, 65,537th word for the IDT72T18105, 131,073rd word for the
IDT72T18115 and 262,145th word for the IDT72T18125. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 2,049th word for the
IDT72T1845, 4,097th word for IDT72T1855, 8,193rd word for the IDT72T1865,
16,385th word for the IDT72T1875, 32,769th word for the IDT72T1885,
65,537th word for the IDT72T1895, 131,073rd word for the IDT72T18105,
262,145th word for the IDT72T18115 and 524,289th word for the IDT72T18125.
Continuing to write data into the FIFO will cause the Programmable Almost-Full
flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW
after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
(D-m) = (2,048-m) writes for the IDT72T1845, (4,096-m) writes for the
IDT72T1855, (8,192-m) writes for the IDT72T1865, (16,384-m) writes for the
IDT72T1875, (32,768-m) writes for the IDT72T1885, (65,536-m) writes for the
IDT72T1895, (131,072-m) writes for the IDT72T18105, (262,144-m) writes
for the IDT72T18115 and (524,288-m) writes for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, (D-m) = (4,096-m) writes for the
IDT72T1845, (8,192-m) writes for the IDT72T1855, (16,384-m) writes for the
IDT72T1865, (32,768-m) writes for the IDT72T1875, (65,536-m) writes for the
IDT72T1885, (131,072-m) writes for the IDT72T1895, (262,144-m) writes for
the IDT72T18105, (524,288-m) writes for the IDT72T18115 and (1,048,576-m)
writes for the IDT72T18125. The offset “m” is the full offset value. The default
setting for these values are stated in the footnote of Table 2. This parameter is
also user programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 2,048 writes
for the IDT72T1845, 4,096 writes for the IDT72T1855, 8,192 writes for the
IDT72T1865, 16,384 writes for the IDT72T1875, 32,768 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,072 writes for the
IDT72T18105, 262,144 writes for the IDT72T18115 and 524,288 writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,096
writes for the IDT72T1845, 8,192 writes for the IDT72T1855, 16,384 writes for
the IDT72T1865, 32,768 writes for the IDT72T1875, 65,536 writes for the
IDT72T1885, 131,072 writes for the IDT72T1895, 262,144 writes for the
IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for
the IDT72T18125, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program-
mable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 1,026th word for the IDT72T1845, 2,050th word for IDT72T1855,
4,098th word for the IDT72T1865, 8,194th word for the IDT72T1875, 16,386th
word for the IDT72T1885, 32,770th word for the IDT72T1895, 65,538th word
for the IDT72T18105, 131,074th word for the IDT72T18115 and 262,146th
word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are
selected, (D/2 + 2) = the 2,050th word for the IDT72T1845, 4,098th word for
IDT72T1855, 8,194th word for the IDT72T1865, 16,386th word for the
IDT72T1875, 32,770th word for the IDT72T1885, 65,538th word for the
IDT72T1895, 131,074th word for the IDT72T18105, 262,146th word for the
IDT72T18115 and 524,290th word for the IDT72T18125. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (2,049-m) writes for the IDT72T1845,
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