STAC9750 Datasheet, PDF (48/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
Bit(s)
15:2
1
0
Table 30. GPIO Pin Configuration Register
Access Reset Value
Read Only
0
Read / Write
1
Read / Write
1
Name
Reserved
GC1
GC0
Description
Bit not used, should read back 0
0 = GPIO1 configured as output
1 = GPIO1 configured as input
0 = GPIO0 configured as output
1 = GPIO0 configured as input
6.5.19.
GPIO Pin Polarity/Type Register (4Eh)
Default: FFFFh
D15
D14
D13
D12
D11
D10
D9
D8
Reserved
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GP1
(GPIO1)
GP0
(GPIO0)
Table 31. GPIO Pin Polarity/Type Register
Bit(s) Access Reset Value Name
Description
15:2 Read Only
0
Reserved Bit not used, should read back 0
1 Read / Write
1
GP1
0 = GPIO1 Input Polarity Inverted, CMOS output drive.
1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive.
0 Read / Write
1
GP0
0 = GPIO0 Input Polarity Inverted, CMOS output drive.
1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.
6.5.20.
GPIO Pin Sticky Register (50h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
Reserved
D7
D6
D5
D4
D3
D2
D1
Reserved
GS1
(GPIO1)
Table 32. GPIO Pin Sticky Register
Bit(s)
15:2
1
0
Access Reset Value
Read Only
0
Read / Write
0
Read / Write
0
Name
Reserved
GS1
GS0
Description
Bit not used, should read back 0
0 = GPIO1 Non Sticky configuration.
1 = GPIO1 Sticky configuration.
0 = GPIO0 Non Sticky configuration.
1 = GPIO0 Sticky configuration.
D8
D0
GS0
(GPIO0)
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
48
STAC9750/9751
V 5.8 103106