STAC9750 Datasheet, PDF (47/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
Table 28. SPDIF Control (Continued)
Bit(s) Reset Access
10:4 0 Read & Write
3
0 Read & Write
2
0 Read & Write
1
0 Read & Write
0
0 Read & Write
Name
CC[6, 0]
PRE
COPY
/AUDIO
PRO
Description (note 1-2)
Category Code is defined by the IEC standard or as appropriate by
media.
0 = 0 µsec Pre-emphasis
1 = Pre-emphasis is 50/15 µsec
0 = Copyright not asserted
1 = Copyright is asserted
0 = PCM data
1 = Non-Audio or non-PCM format
0 = Consumer use of the channel
1 = Professional use of the channel
1. If pin 48 is held high at powerup, 28h D2 will be low indicating no SPDIF available and the regis-
ter 3Ah will then read back 0000h. Pin 48: To Enable SPDIF, use an 1 KΩ-10 KΩ external pull-
down. To Disable SPDIF, use an 1 KΩ-10 KΩ external pullup. Do NOT leave Pin 48 floating.
2. Bits D15, D13-D00 of this register cannot be written to without first setting Reg 2Ah bit D2 = 0
(SPDIF disabled) and Register 28h bit D2 = 1 (SPDIF available).
6.5.17.
Extended Modem Status and Control Register (3Eh)
Default: 0100h
D15
D14
D13
D12
D11
D10
D9
Reserved
D7
D6
D5
D4
D3
D2
D1
Reserved
Table 29. Extended Modem Status and Control
Bit(s)
15:9
8
7:1
0
Access Reset Value
Read Only
0
Read / Write
1
Read Only
0
Read Only
0
Name
Reserved
PRA
Reserved
GPIO
Description
Bit not used, should read back 0
0 = GPIO powered up / enabled
1 = GPIO powered down / disabled
Bit not used, should read back 0
0 = GPIO not ready (powered down)
1 = GPIO ready (powered up)
D8
PRA
D0
GPIO
6.5.18.
GPIO Pin Configuration Register (4Ch)
Default: 0003h
D15
D14
D13
D12
D11
D10
D9
D8
Reserved
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
GC1
(GPIO1)
GC0
(GPIO0)
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
47
STAC9750/9751
V 5.8 103106