STAC9750 Datasheet, PDF (45/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
6.5.13.
6.5.12.4. SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
SPSA[1,0]
00
01
10
11
Table 25. Slot assignment relationship between SPSA1 and SPSA0
Slot Assignment
3&4
7&8
6&9
10 & 11
Comments
SPDIF source data slot assignment
2-channel CODEC primary default
4-channel CODEC primary default
6-channel CODEC primary default
The STAC9750/9751 are AMAP compliant with the following table.
Table 26. STAC9750/9751 AMAP compliant
CODEC
ID
00
01
10
11
Function
2-channel Primary w/SPDIF
2-channel Dock CODEC w/SPDIF
+2-channel Surr w/ SPDIF
+2-channel Cntr/LFE w/ SPDIF
SPSA = 00 SPSA = 01 SPSA = 10
3&4
7 & 8*
6&9
3&4
7&8
6 & 9*
3&4
7&8
6 & 9*
3&4
7&8
6&9
Note: * is the default slot assignment
SPSA = 11
10 & 11
10 & 11
10 & 11
10 & 11*
PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs are controlled by the value in these read/write reg-
isters that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in
Hertz (Hz). In VRA mode (register 2Ah bit D0 = 1), if the value written to these registers is supported,
that value will be echoed back when read, otherwise the closest (higher in the case of a tie) sample
rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample rates are
supported for record and playback. Whenever VRA is set to 0, the PCM rate registers (2Ch and 32h)
will read back with BB80h (48 KHz).
Table 27. Hardware Supported Sample Rates
Sample Rate
8 KHz
11.025 KHz
16 KHz
22.05 KHz
32 KHz
44.1 KHz
48 KHz
SR15-SR0 Value
1F40h
2B11h
3E80h
5622h
7D00h
AC44h
BB80h
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
45
STAC9750/9751
V 5.8 103106