STAC9750 Datasheet, PDF(44/73 Page) Integrated Device Technology

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STAC9750 Datasheet, PDF (44/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

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STAC9750/9751

VALUE-LINE TWO-CHANNEL ACâ97 CODECS

PC AUDIO

6.5.12.

Extended Audio Control/Status (2Ah)

Default: 0400h

D15

D14

Reserved

D13

Reserved

SPSA1

D12

SPSA0

D11

RSRVD

D10

SPCV

SPDIF

Reserved

RSRVD VRA enable

6.5.12.1. Variable Rate Sampling Enable

The Extended Audio Status Control register also contains one active bit to enable or disable the Vari-

able Sampling Rate capabilities of the DACs and ADCs. If the VRA, bit D0, is 1, the variable sample

rate control registers (2Ch and 32h) are active, and âon-demandâ slot data required transfers are

allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.

The STAC9750/9751 supports âon-demandâ slot request flags. These flags are passed from the

CODEC to the ACâ97 controller in every audio input frame. Each time a slot request flag is set (active

low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot

in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable

âon-demandâ data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz trans-

fers and every audio frame will include an active slot request flag and data is transferred every

frame.

For variable sample rate output, the CODEC examines its sample rate control registers, the state of

the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to

determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current

audio input frame for active output slots, which will require data in the next audio output frame.

For variable sample rate input, the tag bit for each input slot indicates whether valid data is present

or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN

(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the

CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is

set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).

6.5.12.2. SPDIF

The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the

SPDIF functionality within the STAC9750/9751. If the SPDIF is set to a 1, then the function is

enabled and when set to a 0 it is disabled.

6.5.12.3. SPCV (SPDIF Configuration Valid)

The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When

SPCV is a 0, it indicates the system configuration is invalid and valid if it is a 1.

IDTâ¢

VALUE-LINE TWO-CHANNEL ACâ97 CODECS

STAC9750/9751

V 5.8 103106

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