STAC9750 Datasheet, PDF (23/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
Figure 13. Start of an Audio Output Frame
SYNC
a s s e rte d
f irs t
SDATA_O UT
b it o f fra m e
SYNC
B IT _ C L K
SDATA_O U T
v a lid
F ra m e
E n d o f p re v io u s a u d io f ra m e
s lo t1 s lo t2
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0s by the AC'97 controller.
When mono audio sample streams are sent from the AC'97 controller, it is necessary that BOTH left
and right sample stream time slots be filled with the same data.
5.1.1.1. Slot 1: Command Address Port
The command port is used to control features and monitor status (see Audio Input Frame Slots 1
and 2) of the STAC9750/9751 functions including, but not limited to, mixer settings and power man-
agement (refer to the Control Register section of this specification).
The control interface architecture supports up to sixty-four 16-bit read/write registers, addressable
on even byte boundaries. Only the even registers (00h, 02h, etc.) are valid. Odd accesses are con-
sidered invalid and return 0000h.
Audio output frame slot 1 communicates control register address and write/read command informa-
tion to the STAC9750/9751.
Bit
19
18:12
11:0
Table 11. Command Address Port Bit Assignments
Description
Read/Write command
Control Register Index
Reserved
Comments
1= read, 0=write
Sixty-four 16-bit locations, addressed on even byte boundaries
Stuffed with 0s
The first bit (MSB) sampled by STAC9750/9751 indicates whether the current control transaction is a
read or a write operation. The following 7 bit positions communicate the targeted control register
address. The trailing 12 bit positions within the slot are Reserved and must be stuffed with 0s by the
AC'97 controller.
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
23
STAC9750/9751
V 5.8 103106