STAC9750 Datasheet, PDF (41/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
6.5.9.
Audio Interrupt (24h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
I4
I3
Reserved
I0
Reserved
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Bit(s)
Reset
Value
R/W
Name
Description
0 = Interrupt is clear
1 = Interrupt is set
15
0 RW
I4
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt enable (I0) status.
An interrupt in the GPI in slot 12 in the AC-Link will follow this bit change when
interrupt enable (I0) is unmasked.
Interrupt Cause
0 = No Interrupt Caused
1 = Change in GPIO input status
14
0 RO
I3
These bits will reflect the general cause of the first interrupt event generated. It
should be read after interrupt status has been confirmed as interrupting. The
information should be used to scan possible interrupting events in proper pages.
13-12 0 RW Reserved Bits not used, should read back 0
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
11
0 RW
I0
The driver should not un-mask the interrupt unless ensured by the AC ‘97 controller
that no conflict is possible with modem slot 12 - GPI functionality. Some AC’97 2.2
compliant controllers do not support audio CODEC interrupt infrastructure. In either
case, S/W should poll the interrupt status after initiating a sense cycle and wait for
Sense Cycle Max Delay to determine if an interrupting event has occurred.
10:0 0 RO Reserved Bits not used, should read back 0
6.5.10.
Powerdown Ctrl/Stat (26h)
Default: 000Fh
D15
D14
D13
D12
D11
D10
D9
D8
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
REF
ANL
DAC
ADC
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
41
STAC9750/9751
V 5.8 103106