STAC9750 Datasheet, PDF (43/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
The Extended Audio ID register is a read-only register, except for bits D5:D4. ID1 and ID0 echo the
configuration of the CODEC as defined by the programming of pins 45 and 46 externally. A returned
00 defines the CODEC as the primary CODEC, while any other code identifies the CODEC as one of
three secondary CODEC possibilities. SDAC = 0 tells the controller that the STAC9750/9751 is a
two-channel CODEC as defined by the Intel specification. The AMAP bit, D9, will return a 1 indicat-
ing that the CODEC supports the optional “AC’97 2.2 compliant AC-link slot to audio DAC map-
pings”. The default condition assumes that 00 are loaded in the DSA0 and DSA1 bits of the
Extended Audio ID (Index 28h). With 00 in the DSAx bits, the CODEC slot assignments are as per
the AC’97 specification recommendations. If the DSAx bits do not contain 00, the slot assignments
are as per the table in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0,
will return a 1 indicating that the CODEC supports the optional variable sample rate conversion as
defined by the AC’97 specification.
Bit Name
15:14 ID [1,0]
13:12
11:10
9
8
7
6
Reserved
Rev[1:0]
AMAP
LDAC
SDAC
CDAC
Access
Read only
Read only
Read only
Read only
Read only
Read only
Read only
Table 24. Extended Audio ID
Reset Value
Function
variable
00 = XTAL_OUT grounded (Note 1)
CID1#, CID0# = XTAL_OUT crystal or floating
00
Reserved
01
Indicates CODEC is AC’97 Rev 2.2 compliant
1
Multi-channel slot support (Always = 1)
0
Low Frequency Effect, not supported (Always=0)
0
Surround DAC, not supported (Always = 0)
0
Center channel, not supported (Always = 0)
DAC slot assignment
5:4 DSA [1,0] Read/Write
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
00
If CID[1:0] = 11 then DSA[1:0] resets to 10
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
3
VRM Read only
0
Variable Sample Rate Mic, not supported (Always = 0)
2
SPDIF Read only
1
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note 2)
1
DRA Read only
0
Double Rate Audio, not supported (Always = 0)
0
VRA Read only
1
Variable sample rates supported (Always = 1)
1. External CID pin status (from analog) these bits are the logical inversion of the pin polarity (pin
45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock source in
primary mode only. Secondary mode can either be through BIT CLK driven or 24 MHz clock
driver with XTAL_OUT floating/shorted.
2. If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not avail-
able. Pin 48: To Enable SPDIF, use an 1 KΩ-10 KΩ external pulldown. To Disable SPDIF, use an
1 KΩ-10 KΩ external pullup. Do NOT leave Pin 48 floating.
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
43
STAC9750/9751
V 5.8 103106