STAC9750 Datasheet, PDF (21/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
5. DIGITAL INTERFACE
5.1. AC-Link Digital Serial Interface Protocol
The STAC9750/9751 communicates to the AC'97 controller via a 5-wire, digital, serial, AC-Link inter-
face, which is a bi-directional, fixed rate, serial PCM digital stream. All digital audio streams, com-
mands and status information are communicated over this point-to-point serial interconnect. The
AC-Link handles multiple input and output audio streams, as well as control register accesses using
a time division multiplexed (TDM) scheme. The AC'97 controller synchronizes all AC-Link data trans-
action. Table 10 shows the data streams available on the STAC9750/9751:
PCM Playback
PCM Record data
Control
Status
Table 10. STAC9750/9751 Available Data Streams
2 output slots
2 input slots
2 output slots
2 input slots
2 Channel composite PCM output stream
2 Channel composite PCM input stream
Control register write port
Control register read port
Synchronization of all AC-Link data transactions is handled by the AC'97 controller. The STAC9750/
9751 drives the serial bit clock onto AC-Link. The AC'97 controller then qualifies with a synchroniza-
tion signal to construct audio frames.
SYNC, fixed at 48 KHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at
12.288 MHz, provides the necessary clocking granularity to support twelve 20-bit outgoing and
incoming time slots. AC-Link serial data is transitioned on each rising edge of BIT_CLK. The receiver
of AC-Link data, STAC9750/9751 for outgoing data and AC'97 controller for incoming data, samples
each serial bit on the falling edges of BIT_CLK.
The AC-Link protocol provides for a special 16-bit (13-bits defined, with 3 Reserved trailing bit posi-
tions) time slot (Slot 0) wherein each bit conveys a “slot-valid” tag for its corresponding time slot
within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding
time slot within the current audio frame has been assigned to a data stream, and contains valid data.
If a slot is tagged invalid, it is the responsibility of the source of the data, (STAC9750/9751 for the
input stream, AC'97 controller for the output stream), to stuff all bit positions with 0s during that slot’s
active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, SYNC, and data signals can be halted by the controller.
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
21
STAC9750/9751
V 5.8 103106