STAC9750 Datasheet, PDF (46/73 Pages) Integrated Device Technology – VALUE-LINE TWO-CHANNEL AC’97 CODECS

STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
PC AUDIO
6.5.14.
PCM DAC Rate (2Ch)
Default: BB80h
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
6.5.15.
PCM LR ADC Rate (32h)
Default: BB80h
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
6.5.16.
SPDIF Control (3Ah)
Default: 2A00h
D15
#V
D7
CC3
D14
DRS
D6
CC2
D13
SPSR1
D5
CC1
D12
SPSR2
D4
CC0
D11
L
D3
PRE
D10
CC6
D2
COPY
D9
CC5
D1
#PCM/AUDIO
D8
CC4
D0
PRO
Register 3Ah is a read/write register that controls SPDIF functionality and manages bit fields propa-
gated as channel status (or sub-frame in the V case). With exception of V, this register should only
be written to when the SPDIF transmitter is disabled (SPDIF bit register 2 Ah is 0). This ensures that
control and status information start up correctly at the beginning of SPDIF transmission. The default
is 2A00h which sets the SPDIF output sample rate at 48 KHz and the normal SPDIF expectations.
Table 28. SPDIF Control
Bit(s) Reset Access
Name
Description (note 1-2)
Validity bit is set indicating each sub-frame’s samples are invalid. If
15 0 Read & Write #V #V is 0, then it indicates that each sub-frame was transmitted and
received correctly by the interface.
14
0
Read Only
DRS 1 = Double Rate SPDIF support (always = 0)
SPDIF Sample Rate.
00 44.1 KHz Rate
13:12 10 Read & Write SPSR[1,0] 01 Reserved
10 48 KHz Rate (default)
11 32 KHz Rate
11 0 Read & Write
L
Generation Level is defined by the IEC standard, or as appropriate.
(Always = 1)
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
46
STAC9750/9751
V 5.8 103106