89HPEB383 Datasheet, PDF (44/264 Pages) Integrated Device Technology – Topics discussed include the following

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4. Addressing > Memory-mapped I/O Space
The response of the bridge to memory-mapped I/O transactions is controlled by the following:
• MS bit in “PCI Control and Status Register” – This bit must be set to allow memory transactions to
be forwarded downstream. If not set, all memory transactions on the PCI bus are forwarded to the
PCIe link. In addition, if not set, all memory requests on the PCIe Interface are completed with an
Unsupported Request status.
• BM bit in “PCI Control and Status Register” – This bit must be set to allow memory transactions to
be forwarded upstream. If this bit is not set, all memory transactions on the PCI bus are ignored.
• VGA_EN bit in “PCI Bridge Control and Interrupt Register”
The PEB383 forwards memory transactions downstream from its PCIe Interface to its PCI Interface if
a memory address is in the range defined by the Memory Base and Memory Limit registers (when the
base is less than or equal to the limit), as shown in Figure 9. A memory transaction on the PCI Interface
that is within this address range, however, is not be forwarded upstream to the PCIe Interface. Any
memory transactions on the PCI Interface that are outside this address range are forwarded upstream to
the PCIe Interface (provided they are not in the address range defined by the set of prefetchable
memory address registers).
Figure 9: Memory-mapped I/O Address Space
Upstream
Primary Interface
Downstream
Memory Base
Memory Limit
PEB383 User Manual
July 25, 2011
Integrated Device Technology, Inc.
Confidential - NDA Required